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(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision Rev. 1.0 Rev. 2.0 Rev. 2.1 Rev. 2.2 Rev. 2.3 Description Initial Issue Revised ISB(max) : 0.5mA => 1.25mA Adding 44-pin TSOP-II Adding 48-ball BGA Revised IDR Deleted L Spec. Added SL Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2 Added ISB1/IDR values when TA = 25 and TA = 40 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Issue Date Apr.19.2006 May.11.2006 Jul.5.2006 Dec.20.2006 Mar.3.2008
Rev. 2.4
Mar.30.2009
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The LY62L25716 is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62L25716 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY62L25716 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible
FEATURES
Fast access time : 45/55/70ns Low power consumption: Operating current : 40/30/20mA (TYP.) Standby current : 2A (TYP.) LL-version 1A (TYP.) SL-version Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I 44-pin 400mil TSOP-II 48-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product Family LY62L25716 LY62L25716(E) LY62L25716(I) Operating Temperature 0 ~ 70 -20 ~ 80 -40 ~ 85 Vcc Range 2.7 ~ 3.6V 2.7 ~ 3.6V 2.7 ~ 3.6V Speed 45/55/70ns 45/55/70ns 45/55/70ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 2A(LL)/1A(SL) 40/30/20mA 2A(LL)/1A(SL) 40/30/20mA 2A(LL)/1A(SL) 40/30/20mA
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION Address Inputs Chip Enable Input Write Enable Input Output Enable Input Lower Byte Control Upper Byte Control Power Supply Ground
FUNCTIONAL BLOCK DIAGRAM
Vcc Vss
A0 - A17 CE#, CE2 WE# OE# LB# UB# VCC
DQ0 - DQ15 Data Inputs/Outputs
DECODER 256Kx16 MEMORY ARRAY
A0-A17
DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte
VSS
I/O DATA CIRCUIT COLUMN I/O
CE# CE2 WE# OE# LB# UB#
CONTROL CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# CE2 NC UB# LB# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC Vss DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0
LY62L25716
TSOP-I
A4 A3 A2 A1 A0 CE# DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE# A17 A16 A15 A14 A13
1 2 3 4 5 6 7
44 43 42 41 40 39 38
A5 A6 A7 OE# UB# LB# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 CE2 A8 A9 A10 A11 A12
LY62L25716
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A B C D E F G H
LB# OE# DQ8 UB#
A0 A3
A1 A4 A6 A7
A2
CE2
CE# DQ0 DQ1 DQ2 DQ3 Vcc
DQ9 DQ10 A5 Vss DQ11 A17 Vcc DQ12 NC DQ14 DQ13 A14 DQ15 NC NC A8 A12 A9
A16 DQ4 Vss A15 DQ5 DQ6 A13 WE# DQ7 A10 A11 NC
1
TSOP II
2
3 4 TFBGA
5
6
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUN RATINGS*
PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read CE# H X X L L L L L L L L CE2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High - Z High - Z ISB,ISB1 High - Z High - Z High - Z High - Z High - Z High - Z ICC,ICC1 High - Z High - Z High - Z DOUT ICC,ICC1 High - Z DOUT DOUT DOUT High - Z DIN ICC,ICC1 High - Z DIN DIN DIN
Write
Note:
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC VIN VSS Output Leakage VCC VOUT VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA Cycle time = Min. - 45 CE# = VIL and CE2 = VIH, ICC - 55 II/O = 0mA - 70 Other pins at VIL or VIH Average Operating Power supply Current Cycle time = 1s CE#0.2V and CE2VCC-0.2V,, ICC1 II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL, ISB other pins at VIL or VIH LL LLE/LLI CE# VCC-0.2V Standby Power *5 SL 25 Supply Current or CE20.2V *5 ISB1 SLE Others at 0.2V or *5 40 SLI VCC - 0.2V SL SLE/SLI
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 5. This parameter is measured at VCC = 3.0V
MIN. 2.7 2.2 - 0.2 -1 -1 2.2 -
TYP. 3.0 2.7 40 30 20 4
*4
MAX. 3.6 VCC+0.3 0.6 1 1 0.4 50 40 30 5
UNIT V V V A A V V mA mA mA mA
-
0.3 2 2 1 1 1 1
1.25 15 20 3 3 10 12
mA A A A A A A
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA = 25, f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 6 8
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* LY62L25716-45 LY62L25716-55 LY62L25716-70 UNIT MIN. MAX. MIN. MAX. MIN. MAX. 45 55 70 ns 45 55 70 ns 45 55 70 ns 25 30 35 ns 10 10 10 ns 5 5 5 ns 15 20 25 ns 15 20 25 ns 10 10 10 ns 45 55 70 ns 20 25 30 ns 10 10 10 ns
SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW
LY62L25716-45 LY62L25716-55 LY62L25716-70 MIN. MAX. MIN. MAX. MIN. MAX. 45 55 70 40 50 60 40 50 60 0 0 0 35 45 55 0 0 0 20 25 30 0 0 0 5 5 5 15 20 25 35 45 60 -
UNIT ns ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA Dout Previous Data Valid tOH Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC Address tAA CE# tACE CE2
LB#,UB# tBA OE# tOE tOLZ tBLZ tCLZ Dout High-Z tOH tOHZ tBHZ tCHZ Data Valid High-Z
Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7
(R)
LY62L25716
Rev. 2.4 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR
256K X 16 BIT LOW POWER CMOS SRAM
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC Address tAW CE# tAS tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR
Data Valid
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8
(R)
LY62L25716
Rev. 2.4 WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)
tWC Address tAW CE# tAS CE2 tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tCW tWR
256K X 16 BIT LOW POWER CMOS SRAM
Data Valid
Notes : 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention SYMBOL TEST CONDITION MIN. VDR CE# VCC - 0.2V or CE2 0.2V 1.5 LL LLE/LLI VCC = 1.5V SL 25 CE# VCC - 0.2V IDR SLE or CE2 0.2V 40 Other pins at 0.2V or VCC-0.2V SLI SL SLE/SLI See Data Retention tCDR 0 Waveforms (below) tR tRC* TYP. 1.0 1.0 0.5 0.5 0.5 0.5 MAX. 3.6 12 16 2.5 2.5 8 10 UNIT V A A A A A A ns ns
Data Retention Current
Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR 1.5V Vcc Vcc(min.) tCDR CE# VIH CE# Vcc-0.2V Vcc(min.) tR VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR 1.5V Vcc Vcc(min.) tCDR CE2 CE2 0.2V VIL VIL Vcc(min.) tR
Low Vcc Data Retention Waveform (3) (LB#, UB# controlled)
VDR 1.5V Vcc Vcc(min.) tCDR LB#,UB# VIH LB#,UB# Vcc-0.2V Vcc(min.) tR VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
48-pin 12mm x 20mm TSOP-I Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
44-pin 400mil TSOP- Package Outline Dimension
SYMBOLS A A1 A2 b c D E E1 e L ZD y
DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0
DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
48-ball 6mm x 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 13
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
LY62L25716 U V - WW XX Y Z
Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0C ~ 70C E : (Extended) -20C ~ +80C I : (Industrial) -40C ~ +85C XX : Power Type LL : Ultra Low Power SL : Special Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type L : 48-pin 12 mm x 20 mm TSOP-I M : 44-pin 400 mil TSOP-II G : 48-ball 6 mm x 8 mm TFBGA
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 14
(R)
LY62L25716
Rev. 2.4
256K X 16 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 15

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